1. Technical Field
The present application relates generally to an integrated circuit device. More specifically, the present application is directed to a system and method for adjusting a voltage for a phase locked loop (PLL) based on temperature. The apparatus and method may be implemented in an integrated circuit device, such as a processor or the like, to both control cooling systems and the voltage of the PLL using a single thermal diode or temperature monitoring device.
2. Description of Related Art
Thermal diodes are often provided in integrated circuit devices to monitor the operating temperature of the integrated circuit device. The thermal diode measures the temperature of the integrated circuit device which is then monitored by a monitoring device, such as a monitoring circuit, system-on-a-chip, or the like, to control operation of the integrated circuit device and/or cooling systems, such as fans or other cooling systems. In this way, dangerous temperature conditions of the integrated circuit device may be avoided by detection and modification of operation of the integrated circuit device and/or cooling systems associated with the integrated circuit device.
Another device typically provided in integrated circuit devices is a phase locked loop. A phase locked loop (PLL) is a closed loop feedback control system that generates an output signal in relation to the frequency and phase of an input, or reference, signal. The PLL automatically responds to the frequency and phase of the input signal by raising or lowering the frequency of a controlled oscillator until it is matched to the reference in both frequency and phase. PLLs are widely used in computing devices, telecommunications systems, radio systems, and other electronic applications where it is desired to stabilize a generated signal or to detect signals in the presence of noise. Since an integrated circuit can hold a complete PLL, the use of PLLs in modern electronic devices is widespread.
PLLs generally include a phase detector circuit, a low pass filter circuit, and a voltage controlled oscillator (VCO) placed in a negative feedback configuration. In addition to these elements, a frequency divider circuit may be provided in the feedback path, the reference signal path, or both, in order to make the PLL's output signal an integer multiple of the reference signal. The phase detector compares the phase of two inputs and outputs a corrective signal to control the VCO such that the phase difference between the two inputs becomes zero. The two inputs are a reference signal and the divided output of the VCO.
Various types of phase detector circuits are known including simple OR gates, four-quadrant multiplier (or “mixer”) circuits, proportional phase detector circuits, and the like. A more complex phase detector uses a simple state machine to determine which of the two signals has a zero-crossing earlier or more often. This brings the PLL into lock even when it is off frequency. This type of phase detector circuit is known as a phase frequency detector (PFD).
The VCO is used to generate a periodic output signal. For example, if the VCO is at approximately the same frequency as the reference signal, and if the phase of the VCO falls behind the phase of the reference signal, the phase detector circuit causes a charge pump of the PLL to charge the control voltage so that the VCO speeds up. Likewise, if the phase of the VCO progresses ahead of the phase of the reference signal, the phase detector circuit causes the charge pump to change the control voltage to slow down the VCO. The low-pass filter smoothes out the abrupt control inputs from the charge pump. Since the frequency of the VCO may be far from the frequency of the reference signal, practical phase detectors may also respond to frequency differences, such as by using a phase frequency detector (PFD), so as to increase the lock-in range of allowable inputs.
As discussed above, most PLLs also include a frequency divider circuit between the VCO and the feedback input to the phase detector circuit in order to produce a frequency synthesizer. This frequency divider circuit may be programmable so as to achieve different output or feedback frequencies of the output signal. Some PLLs may also include a frequency divider circuit between the reference clock input and the reference input to the phase detector circuit. If this frequency divider circuit divides the frequency of the reference signal by M, the inclusion of this frequency divider circuit between the reference clock input and the reference input to the phase detector circuit allows the VCO to multiply the reference signal's frequency by N/M, where N is the multiplier provided by the VCO.
PLLs are used in a number of different ways in modern electronic systems. One use of PLLs is to provide clock signals for processors and other electronic devices. Typically, the clock signals supplied to these processors and other electronic devices come from clock generator PLLs which multiply a lower-frequency reference clock signal up to an operating frequency required by the processor or electronic device. Clock distribution logic may then distribute the clock signal generated by the PLL to various endpoints in the processor or electronic device.
With such clock generation PLLs, and other high-frequency PLLs, the operation of the high-frequency VCO is extremely important. Variability of VCO frequency with respect to temperature, as well as process variation and voltage changes, can have a significant effect on performance, cost, and yield. For example, Complementary Metal Oxide Semiconductor (CMOS) ring oscillators are commonly used for microprocessor clock generation and high speed input/output (I/O). These CMOS oscillators typically have a frequency sensitivity to temperature of about 0.1% to 0.2% per degree Celsius. This temperature variability makes certain intended uses of these CMOS oscillators in high-frequency PLLs not feasible. For example, operation in applications that require extremely wide temperature ranges, such as military specifications (mil-specs) of −55 degrees Celsius to +125 degrees Celsius may not be feasible.